1. Field of the Invention
The present invention relates to a method of performing an etching process, and more particularly, to a method of performing an etching process by using a tri-layer structure.
2. Description of the Prior Art
Poly-silicon is conventionally used as a gate electrode in semiconductor devices, such as the metal-oxide-semiconductor (MOS). However, with a trend toward scaling down the size of semiconductor devices, the conventional poly-silicon gate has faced problems such as inferior performance due to boron penetration and unavoidable depletion effect which increases equivalent thickness of the gate dielectric layer, reduces gate capacitance, and worsens a driving force of the devices.
Currently, in order to meet the shrinking size of the semiconductor MOS, more and more etching technologies are developed. For example, two-exposure-two-etching (2P2E) process or two-exposure-one-etching (2P1E) process are used in forming the contact or the metal interconnect system for connecting the MOS. However, because the small size of the semiconductor structure, there are some problems still need to overcome in current etching process.